Network-on-Chip Architecture Generation Using Arteris FlexNoC

Abstract

Network-on-Chip (NoC) is now the leading communication infrastructure for the contemporary System-on-Chip (SoC) designs as complexity of multicore processors and heterogeneous computing platforms keeps increasing. Conventional bus-based interconnects have several drawbacks like the lack of scalability, high latency, limited bandwidth, and low power efficiency which make them unsuitable for handling the increasing communication needs of advanced semiconductor systems. Hence, scalable and reconfigurable NoC architectures have been widely adopted to facilitate the efficient exchange of data between processing elements, memory units, and peripherals. This paper focuses on the generation of NoC architecture using Arteris FlexNoC which is a commercial tool that is very popular for automated interconnect design and optimization in SoC development. Our proposed method details the definition of system requirements, configuration of network topology, selection of communication protocol, and the generation of optimized interconnect architectures within FlexNoC's automated design environment. In addition, the paper discusses how the choice of topology, routing schemes, and parameter settings can influence the overall performance of the system. Simulation results show that opting for Arteris FlexNoC as a design platform can significantly cut down design complexities, increase scalability, and improve communication efficiency while at the same time reducing latency and power consumption in comparison to old-style interconnect methods. Besides, the automatic generation process allows fast design space exploration and easy verification, so it is a good fit for complicated SoC applications. The results demonstrate the capability of FlexNoC in producing reliable, high-efficiency NoC architectures for embedded and computing systems of tomorrow. To summarize, the proposed method.